Design Verification Engineer – Amazon – Toronto, ON
Location: Toronto, ON | Company: Amazon
Amazon Web Services (AWS) is pushing the boundaries of cloud computing with custom silicon, and their Toronto-based team is growing. This Design Verification Engineer role sits within the Annapurna Labs / Cloud-Scale Machine Learning Acceleration team, where you’ll help shape the hardware behind AWS Inferentia and Trainium — custom-designed machine learning accelerators built for AWS data centres.
This is a hands-on engineering role focused on verifying high-speed I/O and scale-up/out components across a complex SoC. You’ll take ownership of verification plans at the sub-system and chip levels, collaborating with design, architecture, and software teams to ensure hardware-software interfaces are thoroughly validated and tape-out ready.
About the Role: Design Verification Engineer
As a Design Verification Engineer on the Annapurna Labs team, you’ll be responsible for building and executing comprehensive verification environments using state-of-the-art simulation methodologies. Your work will directly influence the reliability and quality of custom silicon that powers some of the world’s most demanding machine learning workloads. You’ll develop robust test scenarios covering system-level flows, critical paths, and corner cases — ensuring designs are production-ready before silicon is committed.
This role demands close cross-functional collaboration. You’ll work alongside design engineers, architects, and software developers to ensure thorough coverage of hardware-software interfaces and cross-module functionality. Coverage closure and verification sign-off will be key milestones you’ll drive toward on every project.
Benefits and Salary
The base salary range for this position in Toronto, ON is $104,900 to $175,100 CAD annually. Amazon’s total compensation package may also include sign-on payments and restricted stock units (RSUs), with final compensation determined by experience, qualifications, and location. Benefits include comprehensive health insurance (medical, dental, vision, prescription, basic life and AD&D), a Registered Retirement Savings Plan (RRSP), a Deferred Profit Sharing Plan (DPSP), paid time off, and additional resources to support health and well-being.
Job Details
📌 Job Type: Full-Time
🏢 Company: Amazon (Amazon Development Centre Canada ULC)
📍 Location: Toronto, ON
🆔 Requisition ID: 10461600
💰 Pay: $104,900 – $175,100 CAD annually
Responsibilities
In this role, you’ll own the full verification lifecycle for high-speed I/O and SoC-level components — from planning through sign-off. Your day-to-day work combines deep technical execution with cross-team collaboration to ensure every design is tape-out ready and meets the highest quality bar for AWS silicon.
- Own and execute verification plans for components at sub-system and chip levels
- Build and implement verification environments using advanced simulation methodologies and industry-standard tools
- Define and create comprehensive test scenarios covering system-level flows, critical paths, and corner cases
- Drive coverage closure and verification sign-off to ensure high-quality, tape-out ready designs
- Collaborate closely with design, architecture, and software teams to ensure thorough coverage of hardware-software interfaces
- Verify cross-module functionality with a strong emphasis on system-wide implications and interactions
Requirements / Skills
The ideal candidate brings a solid foundation in design verification with hands-on experience in constrained-random simulation and testbench development. Amazon values engineers who can take full ownership of complex verification challenges and deliver results in a fast-moving, highly collaborative environment.
- Bachelor’s degree in Electrical Engineering or a related field
- 4+ years of design verification experience using constrained-random simulation techniques such as UVM
- 4+ years of testbench development experience including stimulus, checkers, assertions, and coverage
- Proven experience with test plan development, testbench infrastructure, and design verification workflows
- Experience with C/C++ and Object-Oriented Programming (preferred)
- Familiarity with AMBA protocols such as AHB, APB, or AXI (preferred)
- Experience with interconnect protocols such as PCIe and UCIe (preferred)
How to Apply
To apply, visit the official Amazon job posting using the link below. Make sure your resume is up to date and tailored to highlight your verification and simulation experience before submitting.
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Job Summary & Tips for Applying
Quick Summary & What to Highlight: This Design Verification Engineer role at Amazon in Toronto is perfect for candidates who excel in UVM-based constrained-random verification, testbench development, and SoC-level verification planning. On your resume, emphasize any experience with high-speed I/O verification, AMBA or PCIe protocols, and your ability to drive coverage closure in a fast-paced silicon development environment. If you’ve previously worked on custom silicon, ASIC verification, or machine learning accelerator hardware, make sure to highlight specific achievements and responsibilities that align with this position.
Resume & Application Tips: Before applying, tailor your resume to match the job description. Include keywords like UVM, constrained-random simulation, and testbench infrastructure that appear in the posting. Quantify your achievements where possible (e.g., “achieved 98% functional coverage across 12 SoC sub-systems” or “reduced regression cycle time by 20% through optimized testbench architecture”). Write a brief cover letter expressing your genuine interest in Amazon’s custom silicon team and why you’re excited about this opportunity in Toronto. Double-check your application for spelling errors and ensure your contact information is current.
Interview Preparation: If selected for an interview, research Amazon‘s Leadership Principles, AWS custom silicon roadmap (Inferentia, Trainium), and the Annapurna Labs team beforehand. Prepare specific examples using the STAR method (Situation, Task, Action, Result) to demonstrate your verification planning and coverage closure skills. Common questions may include scenarios about debug strategies, testbench architecture decisions, and handling cross-team dependencies. Dress appropriately for a technology and engineering environment, arrive 10–15 minutes early (or be punctual for virtual interviews), and bring copies of your resume. Prepare thoughtful questions about the team’s verification methodology, current chip development cycle, and opportunities for growth. After the interview, send a thank-you email within 24 hours reiterating your interest in the position.
